-- <File header - VHDL file>
-- Project: pAVR (pipelined AVR). It's a deep pipeline implementation of 
--    Atmel's AVR microcontroller architecture. pAVR's 6 pipeline stages make
--    it run about 3 times faster than the Atmel's core - in terms of clock 
--    frequency and MIPS.
-- Version: 0.50
-- Date: 29 Dec 2004
-- Author: Doru Cuturela, doruu@yahoo.com, geocities.com/doruu
-- License: GNU GPL
-- </File header - VHDL file>



-- <File info - VHDL file>
-- This file contains:
--    - Type conversion routines often used throughout the other source files in
--       this project
--    - Basic arithmetic functions
--       *** Multiplication is not yet defined! It will be defined here.
--    - Sign and zero-extend functions
--    - Vector comparision function
-- </File info - VHDL file>



-- <File body - VHDL file>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;



package std_util is
   function std_logic_vector_to_int(vec: std_logic_vector) return integer;
   function std_logic_vector_to_nat(vec: std_logic_vector) return natural;
   function int_to_std_logic_vector(i, len: integer) return std_logic_vector;

   function "+"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector;
   function "+"(a: std_logic_vector; b: integer) return std_logic_vector;
   function "-"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector;
   function "-"(a: std_logic_vector; b: integer) return std_logic_vector;

   function sign_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector;
   function zero_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector;

   function cmp_std_logic_vector(a: std_logic_vector; b: std_logic_vector) return std_logic;
end;



package body std_util is

   function std_logic_vector_to_int(vec: std_logic_vector) return integer is
      variable i: integer;
   begin
      i := conv_integer(vec);
      return(i);
   end;


   function std_logic_vector_to_nat(vec: std_logic_vector) return natural is
      variable tmp: std_logic_vector(vec'length downto 0);
      variable n: natural;
   begin
      assert (vec'length < 32)
         report "Error: vector length > 31 in function `std_logic_vector_to_nat'."
         severity failure;
      tmp := '0' & vec;
      n := conv_integer(tmp);
      return(n);
   end;


   function int_to_std_logic_vector(i, len: integer) return std_logic_vector is
      variable r: std_logic_vector(len - 1 downto 0);
      variable r1: std_logic_vector(len downto 0);
   begin
      r1 := conv_std_logic_vector(i, len + 1);
      r := r1(len - 1 downto 0);
      return(r);
   end;


   function "+"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector is
   begin
      return(signed(a) + signed(b));
   end;


   function "+"(a: std_logic_vector; b: integer) return std_logic_vector is
   begin
      return(signed(a) + b);
   end;


   function "-"(a: std_logic_vector; b: std_logic_vector) return std_logic_vector is
   begin
      return(signed(a) - signed(b));
   end;


   function "-"(a: std_logic_vector; b: integer) return std_logic_vector is
   begin
      return (signed(a) - b);
   end;


   function sign_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector is
      variable r: std_logic_vector(wxtd - 1 downto 0);
   begin
      assert (a'length <= wxtd)
         report "Error: vector length > extended vector length in function `sign_extend'."
         severity failure;
      for i in 0 to a'length-1 loop
         r(i) := a(i);
      end loop;
      for i in a'length to wxtd - 1 loop
         r(i) := a(a'length - 1);
      end loop;
      return r;
   end;


   function zero_extend(a: std_logic_vector; wxtd: natural) return std_logic_vector is
      variable r: std_logic_vector(wxtd - 1 downto 0);
   begin
      assert (a'length <= wxtd)
         report "Error: vector length > extended vector length in function `sign_extend'."
         severity failure;
      for i in 0 to a'length-1 loop
         r(i) := a(i);
      end loop;
      for i in a'length to wxtd - 1 loop
         r(i) := '0';
      end loop;
      return r;
   end;


   function cmp_std_logic_vector(a: std_logic_vector; b: std_logic_vector) return std_logic is
      variable r: std_logic;
   begin
      assert (a'length = b'length)
         report "Error: vectors don't have the same length in function `cmp_std_logic_vector'."
         severity failure;
      r := '1';
      for i in 0 to a'length - 1 loop
         if (a(i) /= b(i)) then
            r := '0';
         end if;
      end loop;
      return r;
   end;

end;
-- </File body - VHDL file>